You will be part of a team that designs forward error correction (FEC) schemes for optical coherent transceivers. The FEC scheme is one of most critical parts in transceivers, because it allows error free communications.
These blocks are implemented in hardware (ASICs) using a Hardware Description Language (HDL). So, reliability and validation of these blocks is critical.
This job gives you the opportunity to work on some of the most advanced FEC schemes in the world together with very talented people, so we expect exceptional engineers and scientists.
Solving complex optimization problems is part of the job, so proven experience or skill in this field will be highly valued
We are looking for extremely curios, self-motivated people. It is not mandatory to have experience in error correction schemes : talent and drive are far more important.
For this position you will be focused on the analysis and implementation of state-of-the-art error correction techniques.
The analysis will be based on floating-point and fixed-point simulation platforms. The implementation will be based on HDL such as Verilog or SystemVerilog.