Physical Design Engineer
Cordoba, AR
hace 3 días

About MarvellAt Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology.

Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions.

Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing.

If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.The OpportunityAs a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and add-on tools.

You will have the opportunity to use your extensive design and CAD knowledge to define the whole organization's design methodology and work flow.

Job Responsibilities : The engineer will be responsible for implementing tool flows, developing & defining CAD methodologies, generating scripts.

He / she will be involved in evaluation of tools, the development of new tool flows, and be responsible for place & route / timing closure / backend activities.

The engineer will be coding in scripting languages such as TCL and Unix shell languages. In addition, coding in languages such as awk, perl, and C is possible.

The engineer will be required to perform the following ASIC design tasks : Block level layout implementation and timing closureStatic Timing / Crosstalk Analysis and timing closureSynthesis / Physical SynthesisPower / IR / EM analysisPhysical verification (LVS / DRC / ERC)ECO implementationAppropriate training for all required skills will be provided.

Requirements : 1. Bachelors degree in Electronics, Electronic Engineering, Computer Science, Software, or Telecommunications.

2. Experience- Understanding of chip layout / physical design concepts, methodologies and flows (i.e. floorplanning, power planning, power / IR / EM analysis, custom routing, pad ring etc.

Understanding of static timing and crosstalk / noise analysis and timing closure concepts, methodologies and flows.- Understanding of RTL / gate synthesis concepts, methodologies and flows.

  • Experience with the following areas of physical design : RTL / gate synthesisFloorplanning, place and routeStatic timing / crosstalk analysisPhysical verificationPower / IR / EM analysis- Experience with following layout CAD tools : Synthesis : Design Compiler or GenusPlace & Route : ICC2 or FusionCompiler or InnovusStatic timing : Primetime or TempusThe PerksWith competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture.
  • We’ll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

    Your FutureMarvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance.

    If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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