Physical Design Engineer
Cordoba, AR
hace 4 días

About Marvell At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology.

Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions.

Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing.

If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below. The OpportunityAs a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and add-on tools.

You will have the opportunity to use your extensive design and CAD knowledge to define the whole organization's design methodology and work flow.

The engineer will be responsible for implementing tool flows, developing & defining CAD methodologies, generating scripts.

He / she will be involved in evaluation of tools, the development of new tool flows, and be responsible for place & route / timing closure / backend activities.

The engineer will be coding in scripting languages such as TCL and Unix shell languages. In addition, coding in languages such as awk, perl, and C is possible.

The engineer will be required to perform the following ASIC design tasks : Block level layout implementation and timing closure Static Timing / Crosstalk Analysis and timing closure Synthesis / Physical Synthesis Power / IR / EM analysis Physical verification (LVS / DRC / ERC) ECO implementation Appropriate training for all required skills will be provided.

1. Bachelors degree in Electronics, Electronic Engineering, Computer Sciences, Software, or Telecommunications 2. Experience - Understanding of chip layout / physical design concepts, methodologies and flows (i.

e. floorplanning, power planning, power / IR / EM analysis, custom routing, pad ring etc.) - Understanding of static timing and crosstalk / noise analysis and timing closure concepts, methodologies and flows.

  • Understanding of RTL / gate synthesis concepts, methodologies and flows. - Experience with the following areas of physical design : RTL / gate synthesis Floorplanning, place and route Static timing / crosstalk analysis Physical verification Power / IR / EM analysis - Experience with following layout CAD tools : Synthesis : Design Compiler or Genus Place & Route : ICC2 or FusionCompiler or Innovus Static timing : Primetime or Tempus
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